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d a t a sh eet product speci?cation supersededs data of 1996 jul 23 file under integrated circuits, ic02 1996 nov 19 integrated circuits TDA8046 multi-mode qam demodulator
1996 nov 19 2 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 contents 1 features 2 application 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 functional description of the individual blocks 7.1.1 quadrature demodulator and half nyquist filter 7.1.2 equalizer 7.1.3 lock detector 7.1.4 carrier recovery 7.1.5 clock recovery 7.1.6 agc 7.1.7 offset control 7.1.8 loop amplifiers 7.1.9 output formatter 7.1.10 boundary scan 7.1.11 i 2 c-bus interface 7.1.12 i 2 c-bus write parameters 7.1.13 i 2 c-bus read parameters 8 limiting values 9 thermal characteristics 10 demodulator and half nyquist filter characteristics 11 lock detector characteristics 12 carrier recovery characteristics 13 clock recovery characteristics 14 agc characteristics 15 integrated loop amplifiers characteristics 16 characteristics of digital inputs and outputs 17 package outline 18 soldering 18.1 introduction 18.2 reflow soldering 18.3 wave soldering 18.4 repairing soldered joints 19 definitions 20 life support applications 21 purchase of philips i 2 c components
1996 nov 19 3 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 1 features different modulation schemes: 4, 16, 32, 64 and 256-qam digital demodulator and square root raised cosine nyquist filter with roll-off of 15% or 20% high performance adaptive equalizer (no training sequence needed) digital detectors for generation of required control voltages for carrier recovery, clock recovery and agc digital-to-analog converters and operational amplifiers allowing high flexibility for selection of the (pll) loop time constants high maximum symbol rate (r s ) of 7 msymbols/s input format: straight binary or 2s complement (up to 9 bits, ttl compatible) output format: 8-bit wide bus (cmos compatible) i 2 c-bus interface to initialize and monitor the demodulator. when no i 2 c-bus usage; 64-qam, 20% roll-off factor in default mode 5 v peripheral and analog supply voltage 3.3 v core supply voltage boundary scan test. 2 application demodulation for digital cable tv and cable modem. 3 quick reference data notes 1. the supply currents are specified for the maximum symbol frequency. 2. the implementation loss (il) of the demodulator is defined as the distance between the measured and theoretical ber curve as function of signal-to-noise ratio at a ber = 10 - 6 for a back-to-back measurement at the if frequency. this performance depends on the chosen loop parameters (see application notes ). 4 ordering information symbol parameter conditions min. typ. max. unit v ddd(core) core supply voltage 3.00 3.30 3.60 v v ddd digital peripheral supply voltage 4.75 5.00 5.25 v v dda analog supply voltage 4.75 5.00 5.25 v i ddd(core) core supply current v ddd(core) = 3.3 v; note 1 - 100 - ma i ddd digital peripheral supply current v ddd = 5 v; note 1 - 14 - ma i dda analog supply current v dda = 5 v; note 1 - 16 - ma r s symbol rate -- 7 msym/s il implementation loss note 2 - 0.7 - db a nyquist roll-off (programmable) - 15 or 20 - % snr lock signal-to-noise ratio for locking a 64-qam constellation 21 -- db signal-to-noise ratio for locking a 256-qam constellation 27 -- db type number package name description version TDA8046h qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2
1996 nov 19 4 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 5 block diagram d book, full pagewidth 1 to 5, 8 to 11 din0 to din8 square root raised cosine demodulator input represen- tation square root raised cosine coarse agc dac i ref1 v ref 54 53 clock recovery dac i ref2 v ref 58 57 nco control digital phase rotator offset offset control boundary scan test fine agc equalizer fine agc control output formatter 20 to 23 27 to 30 18 do7 to do0 clksdv v carrec v cartc v clkrec v clktc v agc 60 v dda 59 v ssa v agctc i bias carrier recovery dac i ref3 v ref 56 55 52 bias generator v ref i ref1 i ref2 i ref3 analog section clock generator 15 62 4r s 2r s r s to dacs internal clock for digital processing clkadc clk a0 37 scl 35 tms 44 preset 49 clkt 19 tdo 47 tdi 48 trst 42 tck 43 sda 36 i 2 c-bus control 32 clkout 6, 13, 16, 25, 33, 38, 45, 51, 63 TDA8046 mgg198 v ddd1 to 9 7, 12, 14, 17, 24, 26, 31, 34, 46, 50, 61, 64 v ssd1 to 12 41 test1 40 test2 39 test3 fig.1 block diagram.
1996 nov 19 5 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 6 pinning symbol pin i/o description din0 1 i digital input bit 0 (lsb) din1 2 i digital input bit 1 din2 3 i digital input bit 2 din3 4 i digital input bit 3 din4 5 i digital input bit 4 v ddd1 6 supply digital peripheral supply voltage 1 (+5 v) v ssd1 7 supply digital ground 1; for input peripheral and core din5 8 i digital input bit 5 din6 9 i digital input bit 6 din7 10 i digital input bit 7 din8 11 i digital input bit 8 (msb) v ssd2 12 supply digital ground 2; for core and clock buffers v ddd2 13 supply digital supply voltage 2; for core and clock buffers (+3.3 v) v ssd3 14 supply digital peripheral ground 3 clkadc 15 o clock output to adc (4 r s ) v ddd3 16 supply digital peripheral supply voltage 3 (+5 v) v ssd4 17 supply digital ground 4; for core clksdv 18 o clock symbol data valid output clkt 19 i for test purpose only do7 20 o parallel data output (bit 7) do6 21 o parallel data output (bit 6) do5 22 o parallel data output (bit 5) do4 23 o parallel data output (bit 4) v ssd5 24 supply digital peripheral ground 5 v ddd4 25 supply digital peripheral supply voltage 4 (+5 v) v ssd6 26 supply digital ground 6; for core do3 27 o parallel data output (bit 3) do2 28 o parallel data output (bit 2) do1 29 o parallel data output (bit 1) do0 30 o parallel data output (bit 0) v ssd7 31 supply digital peripheral ground 7 clkout 32 i output formatter clock output v ddd5 33 supply digital peripheral supply voltage 5 (+5 v) v ssd8 34 supply digital peripheral ground 8 scl 35 i serial clock input (i 2 c-bus) sda 36 i/o serial data input/output (i 2 c-bus) a0 37 i hardware address input (i 2 c-bus) v ddd6 38 supply digital peripheral supply voltage 6 (+5 v) test3 39 i test input 3 (normally connected to ground) test2 40 i test input 2 (normally connected to ground)
1996 nov 19 6 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 test1 41 i test input 1 input (normally connected to ground) trst 42 i optional asynchronous reset input tck 43 i dedicated test clock input tms 44 i input control signal v ddd7 45 supply digital supply voltage 7; for core (+3.3 v) v ssd9 46 supply digital ground 9; for core tdo 47 o serial test data output tdi 48 i serial test data input preset 49 i set device into default mode input v ssd10 50 supply digital ground 10; for the digital section of the analog block v ddd8 51 supply digital supply voltage 8; for the digital section of the analog block (+5 v) i bias 52 i input bias current for dacs v agctc 53 o inverted operational ampli?er input voltage for loop ?ltering v agc 54 o analog output voltage for agc v cartc 55 o inverted operational ampli?er input voltage for carrier recovery loop ?ltering v carrec 56 o analog output voltage for carrier recovery v clktc 57 o inverted operational ampli?er input voltage for clock recovery loop ?ltering v clkrec 58 o analog output voltage for clock recovery v ssa 59 supply analog ground v dda 60 supply analog supply voltage (+5 v) v ssd11 61 supply digital ground 11; for clock clk 62 i clock input (4 r s ) v ddd9 63 supply digital supply voltage 9; for clock v ssd12 64 supply digital peripheral ground 12 symbol pin i/o description
1996 nov 19 7 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 handbook, full pagewidth TDA8046 mgg197 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 tdi tdo v ssd9 v ddd7 tms tck trst test1 test2 test3 v ddd6 a0 sda scl v ssd8 v ddd5 din0 din1 din2 din3 din4 v ddd1 v ssd1 din5 din6 din7 din8 v ssd2 v ddd2 v ssd3 clkadc v ddd3 v ssd12 v ddd9 clk v ssd11 v dda v ssa v clkrec v clktc v carrec v cartc v agc v agctc i bias v ddd8 v ssd10 preset v ssd4 clksdv clkt do7 do6 do5 do4 v ssd5 v ddd4 v ssd6 do3 do2 do1 do0 v ssd7 clkout fig.2 pin configuration.
1996 nov 19 8 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7 functional description figure 3 shows the application of the TDA8046 multi-mode qam demodulator. the frequency of the if signal (if qam ) is down converted to a frequency that equals the symbol rate (r s ) by a mixer which is driven from a local oscillator with a frequency of f car =f if +r s . after low pass filtering this baseband signal is applied to an external 8 or 9-bit adc. for 256-qam, a 9-bit adc is preferred, for the other modes an 8-bit adc is sufficient. the multi-mode qam demodulator has digital detectors for agc, carrier recovery and clock recovery. the on-chip dacs translate the detector values to analog control currents which are then integrated by a loop filter. to perform this loop filtering, an operational amplifier is integrated after each dac. the carrier recovery consists of a two-loop system. the outer loop is shown in fig.3, and controls both phase and frequency at a low speed. the inner loop controls the carrier phase at a high speed (wide loop bandwidth). the agc also consists of two loops; the outer loop is the coarse agc and one inner loop is the fine agc. the recovered symbols are converted into bits according to a demapping scheme and represented at the output in an 8-bit parallel output format. the qam demodulator can be initialized and monitored by the i 2 c-bus interface. fig.3 application with multi-mode qam demodulator. handbook, full pagewidth mgg167 lpf adc f car = f if + r s clock recovery carrier recovery agc do7 to do0 clkout clksdv 8 or 9 bits if qam saw tuner rf signal f clk TDA8046 i 2 c-bus
1996 nov 19 9 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1 functional description of the individual blocks the functional block diagram of the multi-mode qam demodulator is illustrated in fig.1. this section describes the individual blocks in the demodulator. after adaptation for the used input format (2s complement or binary), the input signal is demodulated in the i and q baseband signals which are applied to the inputs of the half-nyquist filter (equals square root raised cosine). to avoid overloading of the adc, an agc detector is placed after the adaptation for the input format. the control value for the clock recovery is generated after half nyquist filtering. the echoes created in the cable network are reduced significantly in the equalizer. the equalizer produces a clean constellation diagram from which the information for the carrier recovery is derived. this constellation is also applied to the output formatter which demaps the transmitted symbols in corresponding bits. the carrier recovery and lock detection functions are based on the equalizer output. the output of the equalizer is applied to an output formatter, which translates the symbol bits to a fec input format. the digital outputs of the clock recovery, agc, and carrier recovery section are converted into currents which are integrated by the loop filters. to make these loop filters active, operational amplifiers are integrated on the chip. the TDA8046 can handle five different digital modulation schemes; 4, 16, 32, 64 and 256-qam. these schemes are selectable via the i 2 c-bus interface. 7.1.1 q uadrature demodulator and half n yquist filter quadrature demodulation is accomplished after selection of the appropriate input format via the i 2 c-bus. the in-phase and quadrature components are both applied to a half nyquist filter. in default mode, this filter gives a 20% roll-off half nyquist shaping. the basic schematic of the quadrature demodulator followed by the half nyquist filter is shown in fig.4. the signs of the multiplication factors in the q-branch can be inverted (i 2 c-bus bit invd). when using an 8-bit adc the lsb of the 9-bit input word should be connected to the positive supply (v ddd ). this ensures a symmetrical 2s complement representation which can be multiplied by - 1 in a correct (2s complement) way. the overall transfer function of the square root raised cosine filters is shown in figs 5 and 6. for characteristics see chapter 10. fig.4 schematic diagram of the quadrature demodulator and half nyquist filter. handbook, full pagewidth half nyquist filter half nyquist filter + 1, 0, - 1, 0 0, - 1, 0, + 1 9 9 din8 to din0 binary or two's complement i i 2 c-bus i 2 c-bus q mgg168 9 i 2 c-bus i 2 c-bus
1996 nov 19 10 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.5 half nyquist receiver filter transfer function (20% roll-off). handbook, full pagewidth 2 5 0 relative gain (db) 01 0.25 0.5 0.75 1.75 1.5 1.25 mbg987 - 5 - 15 - 25 - 35 - 45 - 55 relative frequency ( f ) r s fig.6 half nyquist receiver filter transfer function (15% roll-off). handbook, full pagewidth 2 0 0 0.5 1 1.5 0.25 0.75 1.25 1.75 relative gain (db) - 10 - 20 - 30 - 40 - 50 mgg169 relative frequency ( f ) r s
1996 nov 19 11 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.2 e qualizer this function is realized with a t spaced 12 or 14 taps (selected via the i 2 c-bus) adaptive filter with a feedback part. the equaliser is based on a decision feedback equalizer (dfe) structure with least mean square (lms) coefficient updating algorithm. no training sequence is required. the block schematic of the total equalizer is shown in fig.8. the main tap of the equalizer is adjustable for fine agc function (6 db agc range). the settings of the equalizer taps can be read via the i 2 c-bus. if the equalizer diverges, an alarm bit is set (i 2 c-bus bit aleq) and an automatic reset of the taps can be performed (i 2 c-bus bit ear). to improve acquisition time, the convergence steps of the ffe/dfe parts of the equalizer are programmable via the i 2 c-bus. when the system locks, the steps are automatically modified for optimum performances. besides reading the equalizer tap values, the main tap of the equalizer can also be programmed. after setting the main tap, the other coefficients can be set to zero. the equalizer settings can also be frozen via the i 2 c-bus. the equalizer has been proven to work correctly under bad channel conditions as indicated in table 1. it is guaranteed that all loops (including equalizer) converge at a snr of 21 db for a 64-qam modulation format and 27 db for a 256-qam modulation format. table 1 channel echo pro?le figure 7 represents the qam spectrum seen by the equalizer. it corresponds (in the frequency domain) to the multiplication of a full nyquist spectrum by the impulse response of the channel specified in table 1. delay amplitude phase 3 8 t sym 0.08 130 1 1 8 t sym 0.20 60 2 t sym 0.05 310 4 5 8 t sym 0.10 200 6 7 8 t sym 0.03 200 fig.7 qam spectrum with echo profile as seen by the equalizer. handbook, full pagewidth 1 - 11 - 0.5 0.5 relative frequency relative gain (db) - 0.375 0.375 - 0.125 0.125 - 0.25 0.25 0 - 3 - 5 - 9 - 1 - 7 mgd636 ( f ) r s
1996 nov 19 12 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.8 dfe equalizer structure. handbook, full pagewidth mgg170 feed forward equalizer taps calculation decision feedback equalizer taps calculation input output decision + - 7.1.3 l ock detector the lock detector indicates whether all algorithms in the demodulator are converged or not. for a symbol error rate (at the input of the demodulator) smaller than 2 10 - 2 , the detector will give the indication lock (i 2 c-bus bit lk = 1). for larger symbol error rates, the detector will generate the unlock signal (i 2 c-bus bit lk = 0). it should ne noted that this unlock signal is generated before any other part of the demodulator loses lock. the lock detector is part of the carrier recovery loop, see fig.9. the lock detector threshold (ldt) can be changed with the help of the i 2 c-bus. the estimation algorithm used in the lock detector also provides information about the ser ratio which can be read out via the i 2 c-bus interface. for characteristics see chapter 11. 7.1.4 c arrier recovery the carrier recovery detector consists of a phase-frequency detector (pfd) and phase detector (pd). depending on the mode of operation, the carrier recovery is switched either between the phase frequency (no lock) or the phase detector (lock). the carrier recovery consists of the following two loops: 1. the outer loop; this loop controls the phase and frequency of the incoming qam signal at the if frequency in such a way that the constellation is optimally positioned for detection. 2. the inner loop; the bandwidth of this loop can be large and can therefore reduce the influence of large bandwidth phase noise. a fully digital carrier recovery function is also possible and can be selected via the i 2 c-bus. should this configuration be used, then the external components of the loop filter will not have to be implemented. four different maximum dac output currents can be selected via the i 2 c-bus. the output currents of the dac are defined in such a way that a vco with a behaviour as shown in fig.9 can be connected directly to the output of the integrated operational amplifier. should the vco slope be negative then the sign of the current can be inverted by the i 2 c-bus. figure 10 defines the dac output currents. for characteristics see chapter 12.
1996 nov 19 13 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.9 schematic diagram of the carrier recovery. handbook, full pagewidth mgg171 demodulation and filtering equalizer phase frequency detector phase detector lock 0 dac r s i ref1 i car v ref lock external digital inner loop adc lpf vco if qam i 2 c-bus i 2 c-bus i 2 c-bus i 2 c-bus lock i 2 c-bus
1996 nov 19 14 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.10 definition of the dac currents and the expected frequency behaviour of the vco. i pos = positive output current. i neg = negative output current. i o i pos i neg C () 2 ------------------------------ - = d i o i pos i neg + () i pos i neg C () -------------------------------- - 100 = handbook, full pagewidth dac output current i car digital input - i car 1 / 2 i car - 1 / 2 i car cari = 1 cari = 0 f vco v carrec mgg180
1996 nov 19 15 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.5 c lock recovery the clock recovery function uses the unequalized i and q signals, i.e. the half nyquist filter outputs (see fig.4). the clock recovery section generates a control value each symbol period. as this algorithm is based on the energy maximization, both main and mid symbols are required at the input. consequently, the input data rate is twice the symbol rate. the schematic diagram of this detector is illustrated in fig.11. the clock generator generates the required internal clocks from the vcxo clock signal at 4 r s . the input stage amplifier of this generator enables the designer to supply a low amplitude oscillator signal to the TDA8046. the dac output current range (i clk ) can be varied via the i 2 c-bus. the sign of the output current can also be inverted to adjust for the correct sign of the vcxo slope. for characteristics see chapter 13. fig.11 schematic diagram of the clock recovery. handbook, full pagewidth dac r s i ref3 i clk v ref external clock recovery detector i q to vcxo from vcxo 4r s 2r s r s mgg172 2 4
1996 nov 19 16 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.12 the definition of the dac currents and the expected frequency behaviour of the vcxo for clock recovery. i pos = positive output current; i clk . i neg = negative output current; - i clk . i oclk i pos i neg C () 2 ------------------------------ - = d i oclk i pos i neg + () i pos i neg C () -------------------------------- - 100 = handbook, full pagewidth dac output current i clk digital input - i clk clki = 1 clki = 0 f vcxo v clkrec mgg181 1 / 2 i clk - 1 / 2 i clk
1996 nov 19 17 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.6 agc the agc estimates the mean power based on the digital input signal and relates this to a peak value for a given constellation. to avoid overloading of the adc, this estimation of the peak signals is used to control the agc loop. the implemented agc covers a range of 20 db in gain variance. a schematic diagram of the agc is illustrated in fig.13. if the saw filter does not have sufficient adjacent channel attenuation, the agc threshold can be varied to avoid clipping of the adc. to do this, the threshold is made programmable via the i 2 c-bus (byte ath). table 2 shows that for each mode, a new ath value (on address 08) must be set with the help of the i 2 c-bus. the i 2 c-bus data on address 08 is a factor 16 smaller than the used agc threshold ath. the dac output current range can be varied via the i 2 c-bus interface (bits agca and agcb) and the sign of the current can be inverted (bit agci). the definition of the dac currents and the expected frequency behaviour of the agc is illustrated in fig.14. for characteristics see chapter 14. table 2 agc threshold values mode ath (agc threshold) i 2 c-bus data for address 08 256, 64, 16 and 4-qam 2040 7f 32-qam 1442 5a fig.13 agc schematic diagram. handbook, full pagewidth dac r s i bias i ref2 i ref2 i agc v ref external agc detector bias generator to agc amplifier mgg173 adc i 2 c-bus i 2 c-bus i 2 c-bus din8 to din0
1996 nov 19 18 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.14 definition of the dac currents and the expected frequency behaviour of the agc. i pos = positive output current; i clk . i neg = negative output current; - i clk . i oagc i pos i neg C () 2 ------------------------------ - = d i oagc i pos i neg + () i pos i neg C () -------------------------------- - 100 = handbook, full pagewidth dac output current i agc digital input - i agc agci = 1 agci = 0 gain v agc mgg182 1 / 14 i agc - 1 / 14 i acg
1996 nov 19 19 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.7 o ffset control to compensate offsets in the i and q branch, due to spurious signals at the symbol frequency at the adc input, an offset compensation loop is included. this loop forces the constellation to be symmetrically distributed over its four quadrants. this function can be switched off by i 2 c-bus bit offs. 7.1.8 l oop amplifiers analog switches are integrated to discharge the loop filter capacitors or for test purposes on application boards (a reference voltage equal to the half of the positive supply voltage v dda is available at the output of the amplifier when the switches are closed). the i 2 c-bus bit anas controls the three switches simultaneously. a schematic diagram of the loop amplifier and analog switch is illustrated in fig.15. for characteristics see chapter 15. fig.15 loop amplifier and analog switch. h andbook, halfpage dac v ref external mgg174 i 2 c-bus 7.1.9 o utput formatter the output formatter transforms the detected symbols into bits in accordance with the selected mapping. the TDA8046 has four possible mapping formats which can be selected via the i 2 c-bus interface. the demapping procedure and the corresponding bits are defined in fig.16. after demapping the bits are allocated to the output. this output allocation corresponds to one of the selected demapping schemes. by using the i 2 c-bus, it is possible to obtain the following output formats: 8 bits parallel semi-serial i and q 8 bits multiplexed. the implemented demapping formats and output bit allocation are illustrated in figs 17 to 30. 7.1.10 b oundary scan the TDA8046h offers the possibility of boundary scan test. the ieee standard test access port and boundary scan architecture allows board manufacturers to test board interconnections by using the boundary scan functions. complete information on boundary scan test is available in application note an96048 .
1996 nov 19 20 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.16 schematic diagram of the output formatter. handbook, full pagewidth mgg175 8 do1 to do0 clkscv clkout do7 to do0 clkscv do7 to do0 clkscv clkout i 8 q demapping schemes 1 to 4 mux parallel and semi-serial i 2 c-bus 7.1.10.1 demapping scheme 1; differential decoding fig.17 demapping scheme 1; bit allocation: 256-qam. bit allocation for 256-qam: b5, b4, b3, b2, b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). handbook, full pagewidth mgg193 010110 011110 001110 000110 010111 011111 001111 000111 010101 011101 001101 000101 010100 011100 001100 000100 100110 101110 111110 110110 100111 101111 111111 110111 100101 101101 111101 110101 100100 101100 111100 110100 i q a quadrant b5 b4 b3 b2 b1 b0 010000 011000 001000 000000 010001 011001 001001 000001 010011 011011 001011 000011 010010 011010 001010 000010 100000 101000 111000 110000 100001 101001 111001 110001 100011 101011 111011 110011 100010 101010 111010 110010
1996 nov 19 21 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 bit allocation for 4-qam: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). bit allocation for 64-qam: b5, b4, b3 and b2; b0 = b1 = 0; b7 and b6 differentially decoded (see table 3). fig.18 demapping scheme 1; bit allocation: 4-qam and 64-qam. handbook, full pagewidth mgg183 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 i q a quadrant b5 b4 b3 b2 b quadrant d quadrant c quadrant 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 fig.19 demapping scheme 1; bit allocation: 16-qam and 32-qam. bit allocation for 16-qam: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). bit allocation for 32-qam: not implemented. handbook, full pagewidth mgg184 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 i q a quadrant b5 b4 b quadrant d quadrant c quadrant 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 0
1996 nov 19 22 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.10.2 demapping scheme 2; direct translation fig.20 demapping scheme 2; bit allocation: 256-qam. bit allocation for 256-qam: b7, b6, b5, b4, b3, b2, b1, b0. handbook, full pagewidth mgg195 i q b6 b7 b5 b4 b3 b2 b1 b0 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
1996 nov 19 23 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.21 demapping scheme 2; bit allocation: 64-qam and 32-qam. bit allocation for 64-qam: b7, b6, b5, b3, b2, b1; b4 = b0 = 0. bit allocation for 32-qam: not implemented. handbook, full pagewidth mgg185 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 i q b7 b6 b5 b3 b2 b1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 fig.22 demapping scheme 2; bit allocation: 4-qam and 16-qam. a. bit allocation for 4-qam: b7 and b3; b6 = b5 = b4 = b2 = b1 = b0 = 0. b. bit allocation for 16-qam: b7, b6, b3 and b2; b5 = b4 = b1 = b0 = 0. handbook, full pagewidth mgg186 0 1 0 0 1 1 1 0 i q b7 b6 b3 b2 1 0 1 1 0 0 0 1 0 1 1 0 i q b7 b3
1996 nov 19 24 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.10.3 demapping scheme 3; differential decoding: draft prets 429: 1994 fig.23 demapping scheme 3; bit allocation: 256-qam. bit allocation for 256-qam: b5, b4, b3, b2, b1, b0; b7 and b6 differentially decoded (see table 3). h andbook, full pagewidth mgg194 101100 101101 101001 101000 101110 101111 101011 101010 100110 100111 100011 100010 100100 100101 100001 100000 111000 111001 111101 111100 111010 111011 111111 111110 110010 110011 110111 110110 110000 110001 110101 110100 i q a quadrant b5 b4 b3 b2 b1 b0 000100 000101 000001 000000 000110 000111 000011 000010 001110 001111 001011 001010 001100 001101 001001 001000 010000 010001 010101 010100 010010 010011 010111 010110 011010 011011 011111 011110 011000 011001 011101 011100
1996 nov 19 25 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.24 demapping scheme 3; bit allocation: 4-qam and 64-qam. bit allocation for 4-qam: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). bit allocation for 64-qam: b5, b4, b3 and b2; b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). handbook, full pagewidth mgg187 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 i q a quadrant b5 b4 b3 b2 b quadrant d quadrant c quadrant 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 fig.25 demapping scheme 3; bit allocation: 16-qam. bit allocation for 16-qam: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). handbook, full pagewidth mgg188 0 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 i q a quadrant b5 b4 b quadrant d quadrant c quadrant 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0
1996 nov 19 26 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.26 demapping scheme 3; bit allocation: 32-qam. bit allocation for 32-qam: b5, b4 and b3; b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see table 3). handbook, full pagewidth mgg189 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 1 1 0 i q a quadrant b5 b4 b3 b quadrant d quadrant c quadrant 1 1 0 0 1 0 1 0 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 0 7.1.10.4 demapping scheme 4; direct translation: hp8782b/k03 fig.27 demapping scheme 4; bit allocation: 256-qam. bit allocation for 256-qam: b7, b6, b5, b4, b3, b2, b1, b0. handbook, full pagewidth mgg196 i q b2 b3 b1 b0 b4 b5 b6 b7 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
1996 nov 19 27 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.28 demapping scheme 4; bit allocation: 64-qam. bit allocation for 64-qam: b7, b6, b5, b4, b3 and b2; b1 = b0 = 0. handbook, full pagewidth mgg190 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 i q b2 b3 b4 b5 b6 b7 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 fig.29 demapping scheme 4; bit allocation: 32-qam. bit allocation for 32-qam: b7, b6, b5, b4 and b3; b2 = b1 = b0 = 0. handbook, full pagewidth mgg191 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 i q a quadrant b7 b6 b5 b4 b3 b quadrant d quadrant c quadrant 1 1 0 1 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0
1996 nov 19 28 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 table 3 de?nition of two msbs in modulation schemes 1 and 3 tables 4 and 5 give the output format of the data for semi-serial mode operations. quadrant of currently received symbol quadrant of previously received symbol phase change (degrees) current output bits scheme 1 scheme 3 b7 b6 b7 b6 a a 0 0000 a b 270 1001 a c 180 1111 a d 90 0110 b a 90 0110 b b 0 0000 b c 270 1001 b d 180 1111 c a 180 1111 c b 90 0110 c c 0 0000 c d 270 1001 d a 270 1001 d b 180 1111 d c 90 0110 d d 0 0000 fig.30 demapping scheme 4; bit allocation: 4-qam and 16-qam. a. bit allocation for 4-qam: b7 and b6; b5 = b4 = b3 = b2 = b1 = b0 = 0. b. bit allocation for 16-qam: b7, b6, b5 and b4; b3 = b2 = b1 = b0 = 0. handbook, full pagewidth mgg192 1 0 1 1 0 0 0 1 i q b4 b5 b6 b7 0 1 0 0 1 1 1 0 1 0 0 1 i q b6 b7
1996 nov 19 29 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 table 4 semi-serial format 256, 64 and 32-qam; see note 1 note 1. the semi-serial format is only valid for demapping schemes 1, 3 and 4. table 5 semi-serial format 16-qam and 4-qam; see note 1 note 1. the semi-serial format is only valid for demapping schemes 1, 3 and 4. slot 256-qam 64-qam 32-qam do1 do0 clksdv do1 do0 clksdv do1 do0 clksdv 0s n-1 (7) s n-1 (6) 1 s n-1 (5) s n-1 (4) 1 s n-1 (4) s n-1 (3) 1 1s n-1 (5) s n-1 (4) 1 s n-1 (3) s n-1 (2) 1 s n-1 (2) s n-1 (1) 1 2s n-1 (3) s n-1 (2) 1 s n-1 (1) s n-1 (0) 1 x x 0 3s n-1 (1) s n-1 (0) 1 x x 0 x x 0 4s n (7) s n (6) 1 s n (5) s n (4) 1 s n-1 (0) s n (4) 1 5s n (5) s n (4) 1 s n (3) s n (2)1s n (3) s n (2) 1 6s n (3) s n (2) 1 s n (1) s n (0)1s n (1) s n (0) 1 7s n (1) s n (0) 1 x x 0 x x 0 slot 16-qam 4-qam do1 do0 clksdv do1 do0 clksdv 0s n-1 (3) s n-1 (2) 1 s n-1 (1) s n-1 (0) 1 1s n-1 (1) s n-1 (0) 1 x x 0 2x x 0 xx 0 3x x 0 xx 0 4s n (3) s n (2) 1 s n (1) s n (0) 1 5s n (1) s n (0) 1 x x 0 6x x 0 xx 0 7x x 0 xx 0
1996 nov 19 30 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.11 i 2 c- bus interface the TDA8046 is controlled by an i 2 c-bus. for programming, there is one module address (7 bits) and the r/ w bit for selecting read or write mode. it should be noted that the TDA8046 starts up in accordance with to the settings defined in tables 7, 8 and 9. table 6 slave address table 7 write (r/ w=0) a6 a5 a4 a3 a2 a1 a0 r/ w 000111a0x function add d7 d6 d5 d4 d3 d2 d1 d0 dac current inversion/general 00 agci clki cari oute dem nyq dphr rst demodulator 01 inp rlf outb outa invd conc conb cona dac/offs/switch 02 anas offs agcb agca clkb clka carb cara digital test/output formatter 03 -- - - outf tsel2 tsel1 tsel0 digital loop ?lter b.w. 04 dca7 dca6 dca5 dca4 dca3 dca2 dca1 dca0 digital loop ?lter b.w. 05 fsol -- -- dcb2 dcb1 dcb0 lock detector threshold 06 ldt7 ldt6 ldt5 ldt4 ldt3 ldt2 ldt1 ldt0 lock detector window size 07 -- - - - - ws1 ws0 agc detector threshold 08 ath7 ath6 ath5 ath4 ath3 ath2 ath1 ath0 equalizer mode 09 -- ear ffel edfe effe efc preset equalizer tap ffei 0a ffei07 ffei06 ffei05 ffei04 ffei03 ffei02 ffei01 ffei00 equalizer steps 0b - fstp2 fstp1 fstp0 - dstp2 dstp1 dstp0
1996 nov 19 31 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 table 8 default settings after reset table 9 read (r/ w=1) function add d7 d6 d5 d4 d3 d2 d1 d0 dac current inversion/ general 0001011100 demodulator 01 1 1 0 0 0 0 1 1 dac/offs/switch 02 0 1 0 1 0 1 0 1 digital test/output formatter 03 ---- 0000 digital loop ?lter b.w. 04 0 1 0 0 0 0 0 0 digital loop ?lter b.w. 05 1 ---- 100 lock detector threshold 0600011000 lock detector window size 07 ------ 00 agc detector threshold 0801111111 equalizer mode 09 -- 010000 equalizer tap ffei 0a 0 1 0 0 0 0 0 0 equalizer steps 0b - 000 - 000 function add d7 d6 d5 d4 d3 d2 d1 d0 v carrec (4 bits) 00 ---- cr03 cr02 cr01 cr00 v clkrec (4 bits) 01 ---- cl03 cl02 cl01 cl00 v agc (4 bits) 02 ---- ag03 ag02 ag01 ag00 alarm equalizer/ lock detector 03 --- aleq --- lk ser estimation 04 le7 le6 le5 le4 le3 le2 le1 le0 ffei3 05 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 ffei0 08 b7 b6 b5 b4 b3 b2 b1 b0 dfei1 09 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 dfei7 0f b7 b6 b5 b4 b3 b2 b1 b0 dfei8 10 b7 b6 b5 b4 b3 b2 b1 b0 ffeq3 11 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 ffeq0 14 b7 b6 b5 b4 b3 b2 b1 b0 dfeq1 15 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 dfeq8 1c b7 b6 b5 b4 b3 b2 b1 b0 ffei5 1d b7 b6 b5 b4 b3 b2 b1 b0 ffeq5 1e b7 b6 b5 b4 b3 b2 b1 b0
1996 nov 19 32 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.12 i 2 c- bus write parameters table 10 i 2 c-bus write parameters; 1-bit values ffei4 1f b7 b6 b5 b4 b3 b2 b1 b0 ffeq4 20 b7 b6 b5 b4 b3 b2 b1 b0 if_frequency_shift 21 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 if_frequency_shift 22 ---- fs11 fs10 fs9 fs8 parameter bit value description input format inp 0 2s complement 1 straight binary inversion demodulator invd 0 q-branch = 0 - 1, 0, +1 1 q-branch = 0 + 1, 0, - 1 demodulator dem 0 by-pass mode 1 normal mode half nyquist ?lter nyq 0 ?lter in by-pass mode 1 half nyquist ?lter on roll-off factor rlf 0 15% roll-off 1 20% roll-off digital phase rotator dphr 0 off: pass through mode 1on general reset rst 0 normal operation 1 reset (with automatic return to normal operation) offset offs 0 off 1on outer loop activation (carrier recovery) oute 0 outer loop inactive 1 outer loop active analog switches anas 0 open 1 closed 1st and 2nd-order loop (inner loop) fsol 0 1st-order loop 1 2nd-order loop dac current inversion cari 0 no inversion 1 inversion clki 0 no inversion 1 inversion agci 0 no inversion 1 inversion function add d7 d6 d5 d4 d3 d2 d1 d0
1996 nov 19 33 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 table 11 i 2 c write parameters; 2-bit values equalizer preset 0 normal operation 1 coef?cient to zero (main tap to 1) edfe 0 normal operation 1 freeze coef?cients of dfe part effe 0 normal operation 1 freeze coef?cients of ffe part efc [?ne agc (equalizer freeze centre tap)] 0 normal operation 1 freeze centre tap, no ?ne agc ear 0 automatic reset switched off 1 automatic reset switched on ffel 0 5 taps in ffe part 1 3 taps in ffe part parameter bits description window size (lock detector) ws1 ws0 0 0 256 symbols 0 1 512 symbols 1 0 1024 symbols 1 1 2048 symbols output format outb outa 0 0 scheme 1 0 1 scheme 2 1 0 scheme 3 1 1 scheme 4 dac carrier recovery (maximum current) carb cara 0050 m a 0 1 100 m a 1 0 150 m a 1 1 200 m a dac clock recovery (maximum current) clkb clka 0050 m a 0 1 100 m a 1 0 150 m a 1 1 200 m a dac agc (maximum current) agcb agca 0050 m a 0 1 100 m a 1 0 150 m a 1 1 200 m a parameter bit value description
1996 nov 19 34 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 table 12 i 2 c-bus write parameters; 3-bit values table 13 convergence step for the equalizer (dfe and ffe parts) table 14 i 2 c-bus write parameters; 4-bit values parameter bits description conc conb cona constellation 0 0 0 4-qam 0 0 1 16-qam 0 1 0 32-qam 0 1 1 64-qam 1 0 0 256-qam dstp2 fstp2 dstp1 fstp1 dstp0 fstp0 convergence step (lock = 0) convergence step (lock = 1) 000 2 -13 2 -15 001 2 -13 2 -14 010 2 -13 2 -13 011 2 -12 2 -15 100 2 -12 2 -14 101 2 -12 2 -13 110 2 -12 2 -12 111 2 -11 2 -15 parameter bits description outf tsel2 tsel1 tsel0 output format 0 0 0 0 8 bits in parallel 0 1 1 1 i/q 8 bits multiplexed (equalizer output) 1 x x x semi-serial special test modes 0 x 0 1 do7 to do4 = carrier recovery dac input; do3 to do0 = agc dac input 0 x 1 0 do7 to do6 = ?ne agc; do5 to do0 = clock recovery dac input 0 0 1 1 do7 to do0 = i and q equal input (i/q 8 bits multiplexed format) 0 1 1 1 do7 to do0 = i and q equal output (i/q 8 bits multiplexed format)
1996 nov 19 35 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 7.1.13 i 2 c- bus read parameters table 15 i 2 c-bus read parameter; 1-bit values table 16 i 2 c-bus read parameter; adc carrier recovery; 4-bit value table 17 i 2 c-bus read parameter; adc clock recovery; 4-bit value table 18 i 2 c-bus read parameter; adc agc; 4-bit value table 19 i 2 c-bus read parameter; 8-bit value note 1. the bits le7 to le0 give the number of symbols falling inside the lock detector active areas. the count is made during an observation period (256 to 2048 symbols). to obtain more details about the ser estimation, refer to application note an96048 . table 20 i 2 c-bus read parameter; 12-bit value note 1. the bits fs11 to fs0 indicate the remaining frequency shift of the qam spectrum (if spectrum). this data is useful if the TDA8046h does not use the outer loop of carrier recovery (bit oute of the i 2 c-bus table set to 0). to obtain more details about the frequency shift calculation, refer to the application note an96048 . parameter bit value description lock detect lk 0 no lock 1 lock alarm equalizer aleq 0 normal operation (alarm off) 1 divergence detected (alarm on) parameter bits description adc carrier recovery cr03 cr02 cr01 cr00 b3 b2 b1 b0 carrier recovery: v carrec = 0.25 + 1 16 v ddd (8b3 + 4b2 + 2b1 + b0) v parameter bits description adc clock recovery cl03 cl02 cl01 cl00 b3 b2 b1 b0 clock recovery: v clkrec = 0.25 + 1 16 v ddd (8b3 + 4b2 + 2b1 + b0) v parameter bits description adc agc ag03 ag02 ag01 ag00 b3 b2 b1 b0 agc: v agc = 0.25 + 1 16 v ddd (8b3 + 4b2 + 2b1 + b0) v parameter bits description ser (1) le7 le6 le5 le4 le3 le2 le1 le0 b7 b6 b5 b4 b3 b2 b1 b0 ser = f (b7 to b0) parameter bits description if_freq_shift (1) fs11 to fs0 frequency shift = f (fs11 to fs0)
1996 nov 19 36 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 8 limiting values in accordance with the absolute maximum rating system (iec 134). 9 thermal characteristics 10 demodulator and half nyquist filter characteristics note 1. definition of the power inter-symbol interference: where n conv is the number of coefficients c conv . c conv (k) represent the coefficient resulting from the convolution of the transmission and reception filters (k indicates the k th coefficient). the power isi specified in table 1 has been calculated on a filter resulting from the convolution of the TDA8046 filters and a truncated half-nyquist filter with 57 t/4 taps for the 15% roll-off filter and 41 t/4 taps for the 20% roll-of filter (see application note an96048 - appendix b). symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.3 6.0 v v max maximum voltage on all pins 0 v ddd v p tot total power dissipation t amb =70 c - 1.4 w t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 70 c symbol parameter conditions value unit r th j-a thermal resistance from junction to ambient in free air 50 k/w symbol parameter conditions min. typ. max. unit a roll-off - 15 or 20 - % pass-band ripple - 0.05 - db stop-band ripple see figs 5 and 6 isi power power inter-symbol interference (15% roll-off ?lter) note 1 -- 43 - db power inter-symbol interference (20% roll-off ?lter) note 1 -- 44 - db isi power db () 10 log 2c conv (4k) 2 k1 = n conv 1 C () 2 ? c conv (0) 2 -------------------------------------------------------------------- - =
1996 nov 19 37 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 11 lock detector characteristics 12 carrier recovery characteristics symbol parameter conditions min. typ. max. unit snr lock signal-to-noise ratio to lock the demodulator 4-qam 8 -- db 16-qam 15 -- db 32-qam 18 -- db 64-qam 21 -- db 256-qam 27 -- db symbol parameter conditions min. typ. max. unit carrier recovery detector c arrier recovery : bias current for dac s set to 37.5 m a k d detector constant snr = 21 db for 64-qam constellation - 3i car -m a/rad snr = 27 db for 256-qam constellation - 6.05i car -m a/rad d f car frequency range 0.017r s -- mhz f n(inner) loop bandwidth of inner loop r s = 5 msym/s 10 -- khz f n(outer) loop bandwidth of outer loop -- 0.3f n(inner) khz i zero zero current of dac - 100 - +100 na i car maximum dac output current (programmable) 50 - 200 m a f dac dac sampling rate - r s - mhz c arrier recovery dac output currents during lock i ocarlock mean output current - 1 2 i car -m a d i ocarlock matching of output currents - 2.5 - +2.5 % c arrier recovery dac output currents during unlock i ocarunlock mean output current - i car -m a d i ocarunlock matching of output currents - 2.5 - +2.5 %
1996 nov 19 38 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 13 clock recovery characteristics 14 agc characteristics symbol parameter conditions min. typ. max. unit clock recovery detector c lock recovery : bias current for dac s set to 37.5 m a k d detector constant snr = 21 db for 64-qam constellation; snr = 27 db for 256-qam constellation - 0.24i clk -m a/rad d f clk frequency range 100 -- ppm f n natural frequency - 400 - hz i clk(max) maximum dac output current (programmable) 50 - 200 m a f dac dac sample rate - r s - mhz c lock recovery dac output currents i oclklock mean output current - i clk -m a d i oclklock matching of output currents - 2.5 - +2.5 % symbol parameter conditions min. typ. max. unit agc detector agc detector : bias current for dac s set to 37.5 m a d r agc agc range of detector 20 -- db i zero zero current - 100 - +100 na i agc(max) maximum dac output current (programmable) 50 - 200 m a f dac dac sample rate - r s - mhz agc dac output currents i oagc mean output current in lock - 1 14 i agc -m a unlock - i agc -m a d i oagc matching of output current - 5+5%
1996 nov 19 39 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 15 integrated loop amplifiers characteristics 16 characteristics of digital inputs and outputs v ddd =v dda =5v; v ddd(core) = 3.3 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit integrated loop ampli?ers l oop amplifiers g ol open loop gain - 60 - db g b gain bandwidth product - 1 - mhz v ref reference voltage - 2.5 - v v o output voltage 0.1v dda - 0.9v dda v r l(vssd) load to ground 5 -- k w r l(vddd) load to supply 6.5 -- k w a nalog switches z sw switch impedance closed - 5 - k w open 10 -- m w symbol parameter conditions min. typ. max. unit clock outputs: clkadc and clksdv v ol low level output voltage 0 - 0.1v ddd v v oh high level output voltage 0.9v ddd - v ddd v t clk cycle time 35 -- ns t w pulse width 40 : 60 duty cycle 14 -- ns t r rise time c l =30pf -- 6ns t f fall time c l =30pf -- 6ns r l load resistance 1 -- k w clock input: clk v i(rms) input voltage level (rms value) sine wave 100 -- mv t clk cycle time 35 -- ns t w pulse width 40 : 60 duty cycle 14 -- ns r source source resistance -- 50 w digital inputs: din8 to din0 v il low level input voltage -- 0.8 v v ih high level input voltage 2.0 -- v t su set-up time 15 -- ns t hd hold time 0 -- ns c l load capacitance -- 10 pf
1996 nov 19 40 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 digital outputs: do1 to do0 with respect to clkout for semi-serial mode v ol low level output voltage 0 - 0.1v ddd v v oh high level output voltage 0.9v ddd - v ddd v t od output delay time -- 7ns t ohd output hold time -- 10 ns c l load capacitance additional 2 - 30 pf digital outputs: do7 to do0 with respect to clksdv for 8-bit parallel mode v ol low level output voltage 0 - 0.1v ddd v v oh high level output voltage 0.9v ddd - v ddd v t od output delay time -- 22 ns t ohd output hold time -- 22 ns c l load capacitance additional 2 - 30 pf digital outputs: do7 to do0 with respect to clkout for i/q multiplexed mode v ol low level output voltage 0 - 0.1v ddd v v oh high level output voltage 0.9v ddd - v ddd v t od output delay time -- 22 ns t ohd output hold time -- 22 ns loop ampli?er v o output voltage level 0.1v dda - 0.9v dda g v dc voltage gain (open loop) - 60 - db g b gain bandwidth product 1 -- mhz r l load resistance 5 -- k w symbol parameter conditions min. typ. max. unit
1996 nov 19 41 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.31 definition of the implementation loss. handbook, full pagewidth mbg989 10 - 4 no convergence theory measured snr (db) implementation loss ber fig.32 cmos input data timing diagram. handbook, full pagewidth mgg176 clkadc din 0 to din 8 90% 90% 10% 10% t w t su; dat t hd; dat t clk v oh v ol v ih v il t f t r
1996 nov 19 42 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.33 cmos semi-serial mode timing diagram. handbook, full pagewidth v oh v ol clkout clksdv do1 to do0 t ohd t od v oh v ol v oh v ol t sym slot 3 slot 2 slot 1 slot 0 mgg179 fig.34 cmos 8-bit symbol in parallel mode timing diagram handbook, full pagewidth mgg177 v oh v ol v oh v ol clksdv data output t ohd t od t sym
1996 nov 19 43 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 fig.35 cmos i and q multiplexed timing diagram. handbook, full pagewidth v oh v ol clkout clksdv do7 to do0 t ohd t od v oh v ol v oh v ol t sym iq mgg178
1996 nov 19 44 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 17 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.4 1.2 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p q detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
1996 nov 19 45 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 18 soldering 18.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 18.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 18.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 nov 19 46 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 19 definitions 20 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 21 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 nov 19 47 philips semiconductors product speci?cation multi-mode qam demodulator TDA8046 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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